A 265-μW Fractional-N Digital PLL with Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. In Proceedings of the Symposium on VLSI Circuits, Honolulu, HI, USA, 16–18 June 2010. A 2.2 GHz sub-sampling PLL with 0.16 psrms jitter and −125 dBc/Hz in-band phase noise at 700 μW loop-components power. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, USA, 22–26 February 2015. A 6.75-to-8.25 GHz 2.25 mW 190 fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65 nm CMOS. A 0.65-V 12–16-GHz Sub-Sampling PLL with 56.4-fs rms Integrated Jitter and −256.4-dB FoM. A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL with TDC-Less Hybrid Loop Control. A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop with Bandwidth Tracking. A 0.9–2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL with Loop Bandwidth-Tracking Technique. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers, Philadelphia, PA, USA, 19–21 February 1969. Phase locking as a new approach for tuned integrated circuits. The authors declare no conflict of interest. The overall conceptual block diagram for the proposed system is presented in Figure 1. The all-digital circuit is beneficial for the power saving as it can be fully powered off, after the calibration is done. We design an all-digital FLL (ADFLL) which consists of a digital divider and an adaptive frequency calibration (AFC). Moreover, the sub-sampling-based PLL has the probability to lock at an unwanted frequency, so a frequency-locked loop (FLL) is necessary to be added to avoid this frequency uncertainty. Although the performance of the charge pump is degraded, the gain of the I-path is much smaller than the gain of the P-path, therefore, the noise contribution in the PLL system is much smaller than that of the P-path (the theoretical verification will be implemented in the following sections). The SSCP is kept to compose the I-path, in order to suppress the noise of the VCO by the type-II structure. Hence, the MSSF can take charge of the P-path directly. As mentioned above, the MSSF, in the type-I PLL, can operate well at low voltage without feature limitation. The main objective of this study is to design a dual path type-II SSPLL to reduce the in-band noise with low supply voltage.
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